The present invention relates to electronic package technology, and more particularly to an improved method of power delivery to an electronic package.
A typical electronic package assembly includes an integrated circuit (IC) die, which includes a piece of semiconductor material onto which a specific IC has been fabricated, and an electronic package or substrate to which the IC die is mounted. A typical implementation of an electronic package assembly uses surface mount technology. As depicted in FIG. 1, a prior art electronic package 1, which comprises an integrated circuit die 40 and a supporting substrate 50, is shown mounted to a printed circuit board (PCB) 20. In the case of a flip-chip die, i.e., a die with the integrated circuit facing down against the substrate, the die 40 is mounted onto the substrate layer 50 via controlled collapse chip connect bumps (C4 bumps) 41, which additionally provide the electrical connection between the circuits of the die 40 and substrate layer 50. The substrate 50, in turn, is mounted onto the PCB 20 via solder balls 10, which additionally provide the electrical connection between the circuits of the PCB 20 and the substrate 50. A voltage regulator module (VRM) 5 supplies the power to the package assembly 1. Conductive pathways, which are formed by vias 3, plated-through holes 6 (PTH""s), and horizontal planes 4, are routed throughout the substrate 50 and the PCB 20, and service to carry current from the VRM 5 to the package assembly 1.
One design aspect of the package assembly 1 includes power delivery. The die 40, like any electrical device, needs a clean power supply and reference voltage for efficient operation. The power delivery aspects of the package design can be characterized by DC voltage and AC noise. The perfect power supply delivers the maximum possible DC voltage with no AC noise. The power delivery path from the VRM 5 to the die 40, however, has an inductance associated with it, creating impedance in the power delivery system. FIG. 2 shows a basic circuit diagram reflecting this impedance ZPowerDelivery. During core switching, when a large amount of current ILoad is being drawn by the die load LDie, such as when running a complex application or first turning a computer on, the current change from the initial draw of current causes a large voltage drop VDie at the die load LDie due to the inductance in the power delivery path.
One known method for mitigating this voltage drop is using decoupling capacitors. These capacitors provide circuit decoupling and supply charge to the die, thus, mitigating the voltage drop and impedance. Several stages of decoupling capacitors are desired to keep the impedance of the power delivery in check. Referring back to FIG. 1, decoupling capacitors 30, which are referred to as die side capacitors (DSC""s), are mounted on the substrate 50 adjacent the die 40. Additional decoupling capacitors 7, which are referred to as bulk capacitors, are mounted on the PCB 20. Additional capacitance is provided by capacitance associated with the die 40 itself, which is referred to as on-die capacitance. The bulk capacitors 7 provide the low and mid-frequency decoupling, while the DSC""s 30 and the on-die capacitance provide the high frequency decoupling.
Because it is preferable to minimize an inductive path 31 created between the DSC""s 30 and the die 40, as illustrated in FIG. 3, it is known in the art to place the DSC""s 30 as close to the die 40 as possible. In the case of a flip chip die, however, there are several limitations to the placement of the DSC""s 30. For example, there is a minimum distance that must be maintained between the DSC""s 30 and the die 40, since there is a substrate area surrounding the die 40 where the DSC""s 30 cannot be placed. This problem is exemplified in FIG. 4, which shows a number of traces 115 that are routed through the substrate 50 to the flip chip die 40, and two DSC""s 30 that are mounted on the substrate 50. Because the current from the DSC""s 30 can distort the I/O signals carried by the traces 115 if the DSC""s 30 are located too close to the traces 115, the DSCs 30 must be a sufficient distance from the die 40 to allow the traces 115 to be routed around the DSC""s 30. Not only does this trace routing problem impact how close the DSC""s 30 can be placed in relation to the die 40, it also impacts the number of DSC""s 30 that can be placed on the substrate 50.
The placement and number of the DSC""s 30 are also limited by the number of paths that the DSC""s 30 can utilize to carry current to the die 40, since only a small set of planes 4 and vias 3 can be utilized to achieve the most efficient pathway, as shown in FIG. 3. In addition to these limitations, the size of the DSC""s 30 are limited, since a heat spreader is often placed on top of the die 40, thus limiting the capacitor size to the height of the die 40.